Much of the error between a clock signal and a transmitted parallel data signal arises because of the difference in transmission distance for the two. It has been common practice to minimize this source of error by equalizing the distance traveled by the data and clock signals. Alternatively, an artificial delay can be introduced in one signal by running it through a delay line of suitable length.
These solutions have the disadvantage of being unique for each transmission path and require consideration of variations in the transmission path caused by connectors and other impedance discontinuities. Each transmission path must be individually tailored, and changes in the path require that the compensation be correspondingly modified.
Such solutions work reasonably well in a fixed environment where transmission distances are relatively short, but become burdensome where variable long distances are involved.
Additionally, when the difference in transmission line distance is compensated with artificial means such as a variable delay line, changes in transmission time caused by humidity or other such variables may lead to an out-of-tolerance operation.
The compensation problem is compounded by the fact that many communications links are bi-directional; that is, data may pass in both directions over the data bus. Since most compensation devices are unidirectional, two such devices are required for each bus. This characteristic compounds the difficulty of troubleshooting a bad bus since it will be necessary to determine whether the failure is occurring in the outbound link or the inbound link.
U.S. Pat. No. 3,919,695 discloses a data processing system having a plurality of units each with its own, adjustable clock. The system described is particularly adapted to use in a system having a number of semiconductor chips, each containing the circuitry for developing the clock signal and the appropriate delay. The penalty of 5% additional circuitry dedicated to the clock function is conceded. The approach is acceptable where the delays associated with each functional unit are fixed by the circuit board design, but becomes unwieldy when variable distances between units must be accommodated.
U.S. Pat. No. 4,285,063 discloses a data processing system in which each of the functional units which require clock pulses has an adjustable delay device which accommodates the variable delay associated with the physical location of the unit. Each functional unit has associated with it a variable length delay line which can be manually adjusted to provide the correct delay. Not only does this approach require a tedious manual adjustment of the delay line after the system is assembled, but any change to the system could require the adjustment process to be repeated because of changes in circuit loading as disclosed in the patent.
U.S. Pat. No. 4,426,713 discloses a data processing system which accommodates the difference in signal path delay times by introducing an adjustable artificial delay at the transmitting end of the system. A pilot signal is used to determine the optimum delay for each transmission path. This approach requires additional circuitry and lends itself to transmission in one direction only.
U.S. Pat. No. 4,490,821 is directed to a system for elimination of timing errors due to the differing distances between units of a data processing system. Time domain reflectometry is utilized to make physical measurements of the actual delays associated with the path from the clock buffer and each of the logic cards in a cabinet. Utilizing this measurement, a variable delay device is adjusted to provide the required compensation. This approach requires a separate delay device for each logic card which uses the clock, necessitates the tedious adjustment of the system after manufacture, and cannot be used on bi-directional lines without modification.
U.S. Pat. No. 4,637,018 describes a data processing system in which the skew associated with clock pulses distributed to various units is compensated for by the use of a variable delay device having an adjustable delay for each clock output signal. Again, this approach is feasible where the propagation path remains constant, for example, on a printed circuit board. This becomes quite cumbersome where unpredictable, variable length, delays occur in a system where the physical distance between units is greater than just the separation of circuits on the same card.
It is, of course, recognized that long bus implementations in the prior art can develop independent clock signals at both ends of the bus. This approach requires elaborate buffering and/or resynchronizing circuitry at both ends of the bus and necessarily delays transmission of data. The bus of this invention does not require that the data be delayed and does not require elaborate circuitry at either end of the bus.